Reductions in the size and inherent features of semiconductor devices (e.g., metal-oxide semiconductor (MOS) devices) have enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the transistor and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the transistor. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the transistor, which, assuming other parameters are maintained relatively constant, may allow an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the transistor.
To further enhance the performance of MOS devices, stress may be introduced in the channel region of a MOS device to improve its carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in a source-to-drain direction.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is to grow SiGe stressors in source and drain regions. Such a method typically includes the steps of forming a gate stack on a semiconductor substrate; forming spacers on sidewalls of the gate stack; forming recesses in the silicon substrate along the gate spacers; epitaxially growing SiGe stressors in the recesses; and then annealing. Since SiGe has a greater lattice constant than silicon has, it applies a compressive stress to the channel region, which is located between a source SiGe stressor and a drain SiGe stressor. Similarly, for NMOS devices, stressors that may introduce tensile stresses, such as SiC stressors, may be formed.
The conventional stressor formation processes suffer drawbacks, however. For example, boron is a commonly used p-type impurity for source/drain regions and lightly doped source/drain regions. To reduce sheet resistance, it is preferred that the boron concentration in SiGe stressors is high. However, the addition of boron has the effect of reducing the lattice constant, and thus with a higher boron concentration, the strain introduced by SiGe stressors is relaxed more. In addition, a high boron concentration results in more boron laterally diffused into channel regions, and the short channel characteristics are adversely affected.
FIG. 1 illustrates a conventional scheme for solving the above-discussed problems. A PMOS device includes SiGe stressors 4 formed in substrate 2, wherein each of the SiGe stressors 4 includes a first layer 41 and a second layer 42. second SiGe layers 42 are doped with p-type impurities, while first SiGe layers 41 are not doped. Therefore, first SiGe layers 41 act as sinks (also referred to as a diffusion barrier layer) for absorbing the p-type impurities that are diffused from second SiGe layers 42. The short channel characteristics may thus be improved.
Technical difficulty exists for forming the PMOS device as illustrated in FIG. 1. The formation of first SiGe layers 41 tends to be non-conformal, and thus it is difficult for SiGe to be formed on sidewalls of recesses, in which SiGe stressors 4 are formed. The thickness T of sidewall portions of SiGe layers 41 tends to be low. Without adequate thickness on sidewalls, SiGe layers 41 are less effective as a barrier for preventing a p-type impurity from diffusing into the channel region, and thus the effects are limited. Therefore, improved structures and methods are needed.